EDN

Synopsys : Static timing tool offers a productivity boost

Synopsys, Inc. has announced that the 2007.12 release of its PrimeTime(R) suite has set a new performance standard for both static timing and signal integrity analysis, accelerating turnaround time ...
Design-Reuse

Setup Margin Aware Quick Hold Fixing

Static Timing Analysis (STA) is a key factor to validate while manufacturing a chip, where each design must go for setup and hold validation. In today’s era, technology nodes are shrinking and ...
Design-Reuse

Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow

Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper ...
Semiconductor Engineering

Rapid Timing Constraints Signoff With Automated Constraint Management

Signoff of a system on chip (SoC) or IP design has multiple aspects, but often timing closure is the most challenging. Early use of a static timing analysis (STA) tool is clearly important, and such a ...
Electronic Design

Oh, The Pain (Of Timing Closure At 28 nm)

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...